Field
The present technology relates to methods and apparatuses for improving the biasing of well bias arrangements, which can lower leakage current and overall power consumption of integrated circuits.
Description of Related Art
The p-type well and the n-type well of integrated circuits are biased such that the source/drain-well junction in the p-type well, and the source/drain-well junction in the n-type well, are reverse biased, or at least not forward biased.
For example, an n-type transistor in a p-type well has n+-doped source and drain regions. Because a forward-biased junction is associated with high current and a reverse-biased junction is associated with low current, the junction between the p-type well and the n+-doped drain region of the n-type transistor is reverse biased by applying the lowest available voltage to the p-type well, such as a ground voltage, or the voltage applied to the n+-doped source region of the n-type transistor.
Similarly, a p-type transistor in an n-type well has p+-doped source and drain regions. Again, because a forward-biased junction is associated with high current and a reverse-biased junction is associated with low current, the junction between the n-type well and the p+-doped source region is reverse biased by applying the highest available voltage to the n-type well, such as a supply voltage, or the voltage applied to the p+-doped source region.